Document Outline
- Features
- Options
- Pin Assignment
- 16MB (x16) SDRAM Part Number
- Key Timing Parameters
- General Description
- Table of Contents
- Functional Block Diagram - 1 Meg x 16 SDRAM
- Pin Descriptions
- Functional Description
- Initialization
- Register Definition
- Mode Register
- Burst Length
- Burst Type
- CAS Latency
- Operating Mode
- Write Burst Mode
- Figure 1 Mode Register Definition
- Table 1 Burst Definition
- Figure 2 CAS Latency
- Table 2 CAS Latency
- Commands
- Command Inhibit
- No Operation (NOP)
- Load Mode Register
- Active
- Read
- Write
- Precharge
- Auto Precharge
- Burst Terminate
- Auto Refresh
- Self Refresh
- Truth Table 1 - Commands and DQM Operation
- Operation
- Bank/Row Activation
- READs
- WRITEs
- Precharge
- Power-Down
- Clock Suspend
- Burst Read/Single Write
- Figure 3 Activating a Specific Row in a Specific Bank
- Figure 4 Example
- Figure 5 READ Command
- Figure 6 CAS Latency
- Figure 7 Consecutive READ Bursts
- Figure 8 Random READ Accesses
- Figure 9 READ to WRITE
- Figure 10 READ to WRITE with Extra Clock Cycle
- Figure 11 READ to PRECHARGE
- Figure 12 Terminating a READ Burst
- Figure 13 WRITE Command
- Figure 14 WRITE Burst
- Figure 15 WRITE to WRITE
- Figure 16 Random WRITE Cycles
- Figure 17 WRITE to READ
- Figure 18 WRITE to PRECHARGE
- Figure 19 Terminating a WRITE Burst
- Figure 20 PRECHARGE Command
- Figure 21 Power-Down
- Figure 22 Clock Suspend During WRITE Burst
- Figure 23 Clock Suspend During READ Burst
- Concurrent Auto Precharge
- Figure 24 READ with AUTO PRECHARGE Interrupted by a READ
- Figure 25 READ with AUTO PRECHARGE Interrupted by a WRITE
- Figure 26 WRITE with AUTO PRECHARGE Interrupted by a READ
- Figure 27 WRITE with AUTO PRECHARGE Interrupted by a WRITE
- Truth Table 2 - CKE
- Truth Table 3 - Current State Bank n, Command to Bank n
- Truth Table 4 - Current State Bank n, Command to Bank m
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Specifications and Conditions
- Capacitance
- Electrical Characteristics and Recommended AC Operating Conditions
- AC Functional Characteristics
- Notes
- Initialize and Load Mode Register
- Power-Down Mode
- Clock Suspend Mode
- Auto Refresh Mode
- Self Refresh Mode
- Single Read - Without Auto Precharge
- Read - Without Auto Precharge
- Read - With Auto Precharge
- Alternating Bank Read Accesses
- Read - Full-Page Burst
- Read - DQM Operation
- Single Write - Without Auto Precharge
- Write - Without Auto Precharge
- Write - With Auto Precharge
- Alternating Bank Read Accesses
- Write - Full-Page Burst
- Write - DQM Operation
- 50-Pin Plastic TSOP (400 mil)
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
1
16Mb: x16
IT SDRAM
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
SETUP
HOLD
CL = 3**
-6
166 MHz
5.5ns
2ns
1ns
-7
143 MHz
5.5ns
2ns
1ns
-8A
125 MHz
6ns
2ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
1 Meg x 16
Configuration
512K x 16 x 2 banks
Refresh Count
2K or 4K
Row Addressing
2K (A0-A10)
Bank Addressing
2 (BA)
Column Addressing
256 (A0-A7)
SYNCHRONOUS
DRAM
MT48LC1M16A1 SIT - 512K x 16 x 2 banks
INDUSTRIAL TEMPERATURE
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/sdramds.html
PIN ASSIGNMENT (Top View)
50-Pin TSOP
FEATURES
PC100 functionality
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V 0.3V power supply
Supports CAS latency of 1, 2 and 3
Industrial temperature range: -40C to +85C
OPTIONS
MARKING
Configuration
1 Meg x 16 (512K x 16 x 2 banks)
1M16A1
Plastic Package - OCPL*
50-pin TSOP (400 mil)
T G
Timing (Cycle Time)
6ns (166 MHz)
-6
7ns (143 MHz)
-7
8ns (125 MHz)
-8A
Refresh
2K or 4K with Self Refresh Mode at 64ms
S
Operating Temperature
-40C to +85C
IT
Part Number Example:
MT48LC1M16A1TG-7SIT
Note: The # symbol indicates signal is active LOW.
V
DD
DQ0
DQ1
VssQ
DQ2
DQ3
V
DD
Q
DQ4
DQ5
VssQ
DQ6
DQ7
V
DD
Q
DQML
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
V
DD
Q
DQ11
DQ10
VssQ
DQ9
DQ8
V
DD
Q
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
16MB (X16) SDRAM PART NUMBER
PART NUMBER
ARCHITECTURE
MT48LC1M16A1TG SIT
1 Meg x 16
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
2
16Mb: x16
IT SDRAM
precharge that is initiated at the end of the burst sequence.
The 1 Meg x 16 SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This archi-
tecture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing the alter-
nate bank will hide the PRECHARGE cycles and provide
seamless, high-speed, random-access operation.
The 1 Meg x 16 SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between inter-
nal banks in order to hide precharge time, and the capability
to randomly change column addresses on each clock cycle
during a burst access.
GENERAL DESCRIPTION
The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a dual 512K x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K x
16-bit banks is organized as 2,048 rows by 256 columns by
16 bits. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA selects the bank, A0-A10 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
3
16Mb: x16
IT SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 1 Meg x 16 ................. 3
Pin Descriptions ........................................................ 4
Functional Description ........................................ 5
Initialization ........................................................ 5
Register Definitions ............................................. 5
Mode Register ................................................ 5
Burst Length .............................................. 5
Burst Type ................................................. 5
CAS Latency .............................................. 7
Operating Mode ....................................... 7
Write Burst Mode ..................................... 7
Commands .............................................................. 8
Truth Table 1 (Commands and DQM Operation)
.............. 8
Command Inhibit ............................................... 9
No Operation (NOP) .......................................... 9
Load Mode Register ............................................ 9
Active .................................................................. 9
Read
.................................................................. 9
Write .................................................................. 9
Precharge ............................................................. 9
Auto Precharge .................................................... 9
Burst Terminate ................................................... 9
Auto Refresh ........................................................ 10
Self Refresh .......................................................... 10
Operation ................................................................ 11
Bank/Row Activation ......................................... 11
Reads .................................................................. 12
Writes .................................................................. 18
Precharge ............................................................. 20
Power-Down ....................................................... 20
Clock Suspend .................................................... 21
Burst Read/Single Write ...................................... 21
Concurrent Auto Precharge ................................ 22
Truth Table 2 (CKE)
................................................... 24
Truth Table 3 (Current State, Same Bank)
....................... 25
Truth Table 4 (Current State, Different Bank)
................... 27
Absolute Maximum Ratings .................................... 29
DC Electrical Characteristics and
Operating Conditions ........................................... 29
I
DD
Specifications and Conditions .......................... 29
Capacitance .............................................................. 30
AC Electrical Characteristics (Timing Table) .... 30
Timing Waveforms
Initialize and Load Mode Register ...................... 33
Power-Down Mode ............................................ 34
Clock Suspend Mode .......................................... 35
Auto Refresh Mode ............................................. 36
Self Refresh Mode ............................................... 37
Reads
Read - Single Read ......................................... 38
Read - Without Auto Precharge .................... 39
Read - With Auto Precharge .......................... 40
Alternating Bank Read Accesses .................... 41
Read - Full-Page Burst .................................... 42
Read - DQM Operation ................................. 43
Writes
Write - Single Write ....................................... 44
Write - Without Auto Precharge ................... 45
Write - With Auto Precharge ......................... 46
Alternating Bank Write Accesses ................... 47
Write - Full-Page Burst ................................... 48
Write - DQM Operation ................................ 49
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
4
16Mb: x16
IT SDRAM
11
11
11
RAS#
REFRESH
CONTROLLER
2,048
REFRESH
COUNTER
CAS#
256
256 (x16)
8
COLUMN-
ADDRESS BUFFER
BURST COUNTER
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
256 (x16)
BANK1
MEMORY
ARRAY
(2,048 x 256 x 16)
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
CONTROL
LOGIC
COLUMN
DECODER
COLUMN-
ADDRESS LATCH
8
MODE REGISTER
ROW-
ADDRESS
LATCH
11
ROW
DECODER
11
COMMAND
DECODE
DQ0-
DQ15
A0-A10, BA
16
8
DQML,
DQMH
256
2,048
BANK0
MEMORY
ARRAY
(2,048 x 256 x 16)
ROW
DECODER
ROW-
ADDRESS
LATCH
11
12
ADDRESS
REGISTER
12
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
16
FUNCTIONAL BLOCK DIAGRAM
1 Meg x 16 SDRAM
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
5
16Mb: x16
IT SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
35
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
34
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN
(row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access
in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
18
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
15, 16, 17
WE#, CAS#,
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
RAS#
command being entered.
14, 36
DQML,
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
DQMH
output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH
corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
19
BA
Input
Bank Address Inputs: BA defines to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. BA is also used to
program the twelfth bit of the Mode Register.
21-24, 27-32, 20
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command
(row-address A0-A10) and READ/WRITE command (column-address A0-
A7, with A10 defining AUTO PRECHARGE) to select one location out of
the 512K available in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
2, 3, 5, 6, 8, 9,
DQ0-
Input/ Data I/Os: Data bus.
11, 12, 39, 40, 42,
DQ15
Output
43, 45, 46, 48, 49
33, 37
NC
No Connect: These pins should be left unconnected.
7, 13, 38, 44
V
DD
Q
Supply DQ Power: Provide isolated power to DQs for improved noise immu-
nity.
4, 10, 41, 47
V
SS
Q
Supply DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
1, 25
V
DD
Supply Power Supply: +3.3V 0.3V.
26, 50
V
SS
Supply Ground.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
6
16Mb: x16
IT SDRAM
FUNCTIONAL DESCRIPTION
In general, the SDRAM is a dual 512K x 16 DRAM
that operates at 3.3V and includes a synchronous
interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the 512K x 16-bit
banks is organized as 2,048 rows by 256 columns by 16
bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA
selects the bank, A0-A10 select the row). The address
bits (A0-A7) registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
Prior to normal operation, the SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register defi-
nition, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to V
DD
and V
DD
Q (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to applying any command other than a COM-
MAND INHIBIT or a NOP. Starting at some point
during this 100s period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100s delay has been satisfied, with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Register Definition
MODE REGISTER
The Mode Register is used to define the specific
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 1. The Mode Register is
programmed via the LOAD MODE REGISTER com-
mand and will retain the stored information until it is
programmed again or the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
The Mode Register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown op-
eration or incompatibility with future versions may result.
When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A7 when the burst length is set to two,
by A2-A7 when the burst length is set to four and by A3-
A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
7
16Mb: x16
IT SDRAM
NOTE: 1. For a burst length of two, A1-A7 select the block
of two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2-A7 select the block
of four burst; A0-A1 select the starting column
within the block.
3. For a burst length of eight, A3-A7 select the block
of eight burst; A0-A2 select the starting column
within the block.
4. For a full-page burst, the full row is selected and
A0-A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A7 select the unique
column to be accessed, and Mode Register bit M3
is ignored.
Table 1
Burst Definition
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2 A1 A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A7
Cn, Cn+1, Cn+2
Page
Cn+3, Cn+4...
Not supported
(256)
(location 0-255)
...Cn-1,
Cn...
Figure 1
Mode Register Definition
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleave
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Burst Length
M0
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
M2
M3
M4
M5
M6
M6 - M0
M8
M7
Op Mode
A10
BA
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
8
16Mb: x16
IT SDRAM
will be valid by T2, as shown in Figure 2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
Table 2
CAS Latency
CAS Latency
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to 1, 2 or 3 clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result
of the clock edge one cycle earlier (n + m - 1), and
provided that the relevant access times are met, the
data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is
registered at T0, and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
CAS
CAS
SPEED
LATENCY = 1
LATENCY = 2 LATENCY = 3
-6
50
125
166
-7
40
100
143
-8A
40
77
125
Figure 2
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON'T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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16Mb: x16
IT SDRAM
TRUTH TABLE 1 COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM ADDR
D Q s NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column and start READ burst)
L
H
L
H
L/H
8
Bank/Col
X
4
WRITE (Select bank and column and
L
H
L
L
L/H
8
Bank/Col Valid
4
start WRITE burst)
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or
L
L
L
H
X
X
X
6, 7
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
L
Active
8
Write Inhibit/Output High-Z
H
High-Z
8
following the Operation section; these tables provide
current state/next state information.
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 and BA define the op-code written to the Mode Register.
3. A0-A10 provide row address, and BA determines which bank is made active.
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
the auto precharge feature; BA determines which bank is being read from or written to.
5. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a
"Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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16Mb: x16
IT SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A10 and
BA. See Mode Register heading in Register Definition
section. The LOAD MODE REGISTER command can
only be issued when all banks are idle, and a subsequent
executable command cannot be issued until
t
MRD is
met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA input selects the bank, and the address
provided on inputs A0-A10 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE com-
mand must be issued before opening a different row in
the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA input
selects the bank, and the address provided on inputs
A0-A7 selects the starting column location. The value
on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the READ burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Read
data appears on the DQs, subject to the logic level on
the DQM inputs two clocks earlier. If a given DQM
signal was registered HIGH, the corresponding DQs
will be High-Z two clocks later; if the DQM signal was
registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA input
selects the bank, and the address provided on inputs
A0-A7 selects the starting column location. The value
on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses.
Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level
appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column
location.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent
row access a specified time (
t
RP) after the PRECHARGE
command is issued. Input A10 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, input BA selects the
bank. Otherwise BA is treated as "Don't Care." Once a
bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE com-
mands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable AUTO
PRECHARGE in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE com-
mand.
AUTO PRECHARGE ensures that the PRECHARGE
is initiated at the earliest valid stage within a burst. The
user must not issue another command to the same
bank until the precharge time (
t
RP) is completed. This
is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described for
each burst type in the Operation section of this data
sheet.
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16Mb: x16
IT SDRAM
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated
as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation
of the SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh
is required.
The addressing during an AUTO REFRESH com-
mand is generated by an internal refresh controller.
This means that the address lines are not used to
generate the refresh address, and are "Don't Care".
The 1 Meg x 16 SDRAM requires 2,048 AUTO
REFRESH cycles every 64ms (
t
REF) to ensure that each
row is refreshed. Distributed refresh would be achieved
by providing an AUTO REFRESH command once ev-
ery 31.25s. Burst refresh could be accomplished by
issuing 2,048 AUTO REFRESH commands consecu-
tively at the minimum cycle rate of
t
RC.
To provide a 4K refresh scheme, the refresh rate
would be doubled. Thus, 2,048 AUTO-REFRESH com-
mands distributed every 15.625s would allow the 1
Meg x 16 SDRAM to have a 4K refresh if required. Of
the three types of refreshs options, utilizing the 2,048
cycles every 64ms (31.25s per refresh) provides the
maximum power savings.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become "Don't Care," with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM
provides its own internal clocking, causing it to per-
form its own auto refresh cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to
t
RAS, and may remain in self refresh mode for
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
XSR, because time is required for the completion of
any internal refresh in progress.
Upon exiting self refresh mode, AUTO REFRESH
commands may be issued every 15.625s or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
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16Mb: x16
IT SDRAM
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be
issued to a bank within the SDRAM, a row in that bank
must be "opened." This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE com-
mand) a READ or WRITE command may be issued to
that row, subject to the
t
RCD specification.
t
RCD
(MIN) should be divided by the clock period and
rounded up to the next whole number to determine
the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be issued. For
example, a
t
RCD specification of 20ns with a 125 MHz
clock (8ns period) results in 2.5 clocks rounded to 3.
This is reflected in Figure 4, which covers any case where
2 <
t
RCD (MIN)/
t
CK
3. (The same procedure is used
to convert other specification limits from time units to
clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed, which
results in a reduction of total row access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by
t
RRD.
CS#
WE#
CAS#
RAS#
CKE
CLK
A0-A10
BA
ROW
ADDRESS
HIGH
BANK 0
BANK 1
Figure 3
Activating a Specific Row
in a Specific Bank
Figure 4
EXAMPLE: Meeting
t
RCD (MIN) when 2 <
t
RCD (MIN)/
t
CK
3
CLK
T2
T1
T3
T0
t
COMMAND
NOP
ACTIVE
READ or
WRITE
T4
NOP
RCD
DON'T CARE
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16Mb: x16
IT SDRAM
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and
continue).
Data from any READ burst may be truncated with
a subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a subsequent READ command. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst, or the last desired
data element of a longer burst which is being trun-
cated. The new READ command should be issued x
cycles before the clock edge at which the last desired
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command and AUTO
PRECHARGE is either enabled or disabled for that burst
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic READ commands used in the following
illustrations, AUTO PRECHARGE is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 6 shows general timing
for each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A7
A10
BA
BANK 0
BANK 1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A8-A9
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON'T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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14
16Mb: x16
IT SDRAM
data element is valid, where x equals the CAS latency
minus one. This is shown in Figure 7 for READ latencies
of one, two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer
burst. The 1 Meg x 16 SDRAM uses a pipelined architec-
Figure 7
Consecutive READ Bursts
ture and therefore does not require the 2n rule associ-
ated with a prefetch architecture. A READ command
can be initiated on any clock cycle following a previous
READ command. Full-speed, random read accesses
within a page can be performed as shown in Figure 8.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL n
DON'T CARE
NOP
BANK,
COL b
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
D
OUT
b
READ
X = 0 cycles
NOTE: Each READ command may be to either bank. DQM is LOW.
CAS Latency = 1
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL n
NOP
BANK,
COL b
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
D
OUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL n
NOP
BANK,
COL b
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
D
OUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
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16Mb: x16
IT SDRAM
Figure 8
Random READ Accesses
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
BANK,
COL n
DON'T CARE
D
OUT
n
D
OUT
a
D
OUT
x
D
OUT
m
READ
NOTE: Each READ command may be to either bank. DQM is LOW.
READ
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
D
OUT
a
D
OUT
x
D
OUT
m
READ
READ
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
D
OUT
a
D
OUT
x
D
OUT
m
READ
READ
READ
BANK,
COL a
BANK,
COL x
BANK,
COL m
CAS Latency = 1
CAS Latency = 2
CAS Latency = 3
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16Mb: x16
IT SDRAM
Data from any READ burst may be truncated with
a subsequent WRITE command, and data from a
fixed-length READ burst may be immediately followed
by data from a subsequent WRITE command (subject
to bus turnaround limitations). The WRITE burst may
be initiated on the clock edge immediately following
the last (or last desired) data element from the READ
burst, provided that I/O contention can be avoided. In
a given system design, there may be the possibility that
the device driving the input data would go Low-Z
before the SDRAM DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read
data and the WRITE command.
The DQM input is used to avoid I/O contention as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks (DQM latency is
two clocks for output buffers) prior to the WRITE
DON'T CARE
READ
NOP
NOP
NOP
NOP
DQM
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
D
IN
b
BANK,
COL b
T5
DS
tHZ
t
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
Figure 10
READ to WRITE with
Extra Clock Cycle
Figure 9
READ to WRITE
READ
NOP
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
D
OUT
n
COMMAND
D
IN
b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
command to suppress data-out from the READ. Once
the WRITE command is registered, the DQs will go
High-Z (or remain High-Z) regardless of the state of the
DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated
the READ command. If not, the second WRITE will be
an invalid WRITE. For example, if DQM was LOW
during T4 in Figure 10, then the WRITEs at T5 and T7
would be valid, while the WRITE at T6 would be
invalid.
The DQM signal must be de-asserted (DQM latency
is zero clocks for input buffers) prior to the WRITE
command to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency
allows for bus contention to be avoided without add-
ing a NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
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16Mb: x16
IT SDRAM
Figure 11
READ to PRECHARGE
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not
activated) and a full-page burst may be truncated with
a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
NOTE: DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK a,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
BANK a,
ROW
BANK
(a or all)
DON'T CARE
X = 0 cycles
CAS Latency = 1
X = 1 cycle
CAS Latency = 2
CAS Latency = 3
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
X = 2 cycles
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16Mb: x16
IT SDRAM
Figure 12
Terminating a READ Burst
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
tage of the PRECHARGE command is that it requires
that the command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that AUTO PRECHARGE
was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which
the last desired data element is valid, where x equals the
CAS latency minus one. This is shown in Figure 12 for
each possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
BURST
TERMINATE
NOP
T7
DON'T CARE
NOTE: DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
BURST
TERMINATE
NOP
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
BURST
TERMINATE
NOP
X = 0 cycles
CAS Latency = 1
X = 1 cycle
CAS Latency = 2
CAS Latency = 3
X = 2 cycles
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19
16Mb: x16
IT SDRAM
WRITEs
WRITE bursts are initiated with a WRITE com-
mand, as shown in Figure 13.
The starting column and bank addresses are pro-
vided with the WRITE command and AUTO
PRECHARGE is either enabled or disabled for that
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic WRITE commands used in the follow-
ing illustrations, AUTO PRECHARGE is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z, and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page it will wrap to column 0 and
continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a subsequent WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
Figure 15
WRITE to WRITE
coincident with the new command applies to the new
command. An example is shown in Figure 15. Data n
+ 1 is either the last of a burst of two, or the last desired
of a longer burst. The 1 Meg x 16 SDRAM uses a
pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture. A
WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full-speed,
random write accesses within a page can be performed
as shown in Figure 16.
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
NOP
WRITE
D
IN
n + 1
NOP
BANK,
COL n
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
DON'T CARE
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
WRITE
BANK,
COL n
BANK,
COL b
D
IN
n
D
IN
n + 1
D
IN
b
NOTE:
DQM is LOW. Each WRITE
command may be to any bank.
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A7
A10
BA
BANK 0
BANK 1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A8-A9
Figure 13
WRITE Command
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20
16Mb: x16
IT SDRAM
input data element is registered. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until
t
RP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
tage of the PRECHARGE command is that it requires
that the command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two,
or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that AUTO PRECHARGE
was not activated), and a full-page WRITE burst may
be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be
issued
t
WR after the clock edge at which the last desired
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
a
D
IN
x
D
IN
m
WRITE
WRITE
WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOTE:
Each WRITE command may be to any bank.
DQM is LOW.
Figure 16
Random WRITE Cycles
Figure 17
WRITE to READ
CLK
DQ
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
D
IN
n
D
IN
n + 1
D
OUT
b
READ
NOP
NOP
BANK,
COL b
NOP
D
OUT
b + 1
T4
T5
NOTE:
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 18
WRITE to PRECHARGE
DQM
CLK
DQ
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK a,
COL n
T5
NOP
WRITE
PRECHARGE
NOP
NOP
DIN
n
DIN
n + 1
ACTIVE
t RP
DON'T CARE
BANK
(a or all)
t
WR
NOTE:
DQM could remain LOW in this example if the WRITE burst is a
fixed length of two. Future SDRAMs will require a
t
WR of at least
two clocks.
BANK a,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK a,
COL n
NOP
WRITE
PRECHARGE
NOP
D
IN
n
D
IN
n + 1
ACTIVE
t RP
BANK
(a or all)
t
WR
BANK a,
ROW
NOP
t
WR = 1 CLK (
t
CK
t
WR)
t
WR = 2 CLK (
t
CK <
t
WR)
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21
16Mb: x16
IT SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied
coincident with the BURST TERMINATE command
will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data
applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 19, where data n is
the last desired data element of a longer burst.
Figure 21
POWER-DOWN
Figure 20
PRECHARGE Command
Figure 19
Terminating a WRITE Burst
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
BA
BANK 1
HIGH
BANK 0 and 1
BANK 0 or 1
BANK 0
A0-A9
tRAS
tRCD
tRC
All banks idle
Input buffers gated off
Exit POWER-
DOWN mode
(
)
(
)
(
)
(
)
(
)
(
)
tCKS
< tCKS
COMMAND
NOP
ACTIVE
Enter POWER-
DOWN mode
NOP
CLK
CKE
(
)
(
)
(
)
(
)
DON'T CARE
CLK
DQ
DIN
n
(Data)
T2
T1
T0
COMMAND
ADDRESS
BURST
TERMINATE
WRITE
Next
Command
BANK,
COL n
NOTE: DQMs are low
(Address)
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks (see Figure 20). The bank(s) will be available
for a subsequent row access some specified time (
t
RP)
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, input BA selects the bank. When all
banks are to be precharged, input BA is treated as
"Don't Care." Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
POWER-DOWN
POWER-DOWN occurs if CKE is registered LOW
coincident with a NOP or COMMAND INHIBIT, when
no accesses are in progress (see Figure 21). If POWER-
DOWN occurs when all banks are idle, this mode is
referred to as precharge power-down; if power-down
occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering
power-down deactivates the input and output buff-
ers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-
down state longer than the refresh period (64ms) since
no refresh operations are performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
t
CKS).
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16Mb: x16
IT SDRAM
DQ
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
n
NOP
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
D
IN
n + 1
D
IN
n + 2
NOTE: For this example, burst length = 4 or greater, and DQM
is LOW.
Figure 22
Clock Suspend During WRITE Burst
DON'T CARE
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
CKE
INTERNAL
CLOCK
NOP
Figure 23
Clock Suspend During READ Burst
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, "freezing" the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge are
ignored; any data present on the DQ pins will remain
driven; and burst counters are not incremented as long
as the clock is suspended (see examples in Figures 22
and 23).
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one) regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
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23
16Mb: x16
IT SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with AUTO
PRECHARGE enabled is executing is not allowed by
SDRAMs, unless the SDRAM supports CONCURRENT
AUTO PRECHARGE. Micron SDRAMs support CON-
CURRENT AUTO PRECHARGE. Four cases where
CONCURRENT AUTO PRECHARGE occurs are de-
fined below.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
READ on bank n, CAS latency later. The
PRECHARGE to bank n will begin when the READ
to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank
n will begin when the WRITE to bank m is registered
(Figure 25).
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK n
NOP
NOP
NOP
NOP
D
OUT
a + 1
D
OUT
d
D
OUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
NOTE: DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANK m
CAS Latency = 3 (BANK n)
Figure 24
READ with AUTO PRECHARGE Interrupted by a READ
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
NOP
NOP
NOP
D
IN
d + 1
D
IN
d
D
IN
d + 2
D
IN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
NOTE: 1. DQM is HIGH at T2 to prevent D
OUT
-a+1 from contending with D
IN
-d at T4.
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP - BANK n
t WR - BANK m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON'T CARE
Figure 25
READ with AUTO PRECHARGE Interrupted by a WRITE
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16Mb: x16
IT SDRAM
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
NOP
NOP
NOP
D
IN
a + 1
D
IN
a
NOP
NOP
T7
BANK n
BANK m
ADDRESS
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK m
D
OUT
d
D
OUT
d + 1
CAS Latency = 3 (BANK m)
RP - BANK n
WR - BANK n
Figure 26
WRITE with AUTO PRECHARGE Interrupted by a READ
DON'T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
NOP
NOP
NOP
D
IN
d + 1
D
IN
d
D
IN
a + 1
D
IN
a + 2
D
IN
a
D
IN
d + 2
D
IN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
WR - BANK n
tRP - BANK n
t WR - BANK m
Figure 27
WRITE with AUTO PRECHARGE Interrupted by a WRITE
WRITE with AUTO PRECHARGE
3. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-
out appearing CAS latency later. The PRECHARGE
to bank n will begin after
t
WR is met, where
t
WR
begins when the READ to bank m is registered. The
last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
t
WR is met, where
t
WR
begins when the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
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25
16Mb: x16
IT SDRAM
TRUTH TABLE 2 CKE
(Notes: 1-4)
CKE
n-1
CKE
n
CURRENT STATE
COMMAND
n
ACTION
n
NOTES
L
L
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
L
H
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
Clock Suspend
X
Exit Clock Suspend
7
H
L
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
VALID
Clock Suspend Entry
H
H
See Truth Table 3
NOTE: 1. CKE
n
is the logic state of CKE at clock edge n; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
n
is the command registered at clock edge n and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that
t
CKS is met).
6. Exiting SELF REFRESH at clock edge n will put the device in the all banks idle state once
t
XSR is met. COMMAND
INHIBIT or NOP commands should be issued on any clock edges occurring during the
t
XSR period. A minimum of two NOP
commands must be provided during
t
XSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
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16Mb: x16
IT SDRAM
TRUTH TABLE 3 CURRENT STATE BANK n - COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
L
L
H
H
ACTIVE (Select and activate row)
Idle
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select column and start READ burst)
10
Row Active
L
H
L
L
WRITE (Select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select column and start new READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select column and start READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start new WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
NOTE: 1. This table applies when CKE
n-1
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged and
t
RP has been met.
Row Active: A row in the bank has been activated and
t
RCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank, should be issued on any clock edge occuring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
t
RP is met. Once
t
RP is met,
the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when
t
RCD is met. Once
t
RCD is met,
the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when
t
RP
has been met. Once
t
RP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
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16Mb: x16
IT SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met. Once
t
RC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when
t
MRD has been
met. Once
t
MRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. Once
t
RP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and
READs or WRITEs with AUTO PRECHARGE disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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16Mb: x16
IT SDRAM
TRUTH TABLE 4 CURRENT STATE BANK n - COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
Idle
X
X
X
X
Any command otherwise allowed to bank m
Row Activating,
L
L
H
H
ACTIVE (Select and activate row)
Active or
L
H
L
H
READ (Select column and start READ burst)
7
Precharging
L
H
L
L
WRITE (Select column and start WRITE burst)
7
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 10
Precharge
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 11
Disabled)
L
L
H
L
PRECHARGE
9
Write
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start READ burst)
7, 12
Precharge
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 13
Disabled)
L
L
H
L
PRECHARGE
9
Read
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 8, 14
Precharge)
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 8, 15
L
L
H
L
PRECHARGE
9
Write
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start READ burst)
7, 8, 16
Precharge)
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
L
L
H
L
PRECHARGE
9
NOTE: 1. This table applies when CKE
n-1
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged and
t
RP has been met.
Row Active: A row in the bank has been activated and
t
RCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when
t
RP
has been met. Once
t
RP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
29
16Mb: x16
IT SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
rupted by bank m's burst.
9. Burst in bank n continues as initiated.
10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank
m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m
will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n will begin after
t
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m
will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after
t
WR is met, where
t
WR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
30
16Mb: x16
IT SDRAM
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6) (-40C
T
A
+85C; V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
, V
DD
Q
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2.2
V
DD
+ 0.3
V
22
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.3
0.8
V
22
INPUT LEAKAGE CURRENT:
Any input 0V
V
IN
V
DD
I
I
-5
5
A
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V
V
OUT
V
DD
Q
I
OZ
-10
10
A
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
V
OL
0.4
V
I
DD
SPECIFICATIONS AND CONDITIONS
(Notes: 1, 6, 11, 13) (-40C
T
A
+85C; V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
-6
-7
-8A
UNITS NOTES
OPERATING CURRENT: Active Mode;
I
DD
1
145
140
135
mA
3, 18,
Burst = 2; READ or WRITE;
t
RC =
t
RC (MIN);
19, 26
CAS latency = 3
STANDBY CURRENT: Power-Down Mode;
I
DD
2
2
2
2
mA
26
CKE = LOW; All banks idle
STANDBY CURRENT: Active Mode; CS# = HIGH;
I
DD
3
45
40
35
mA
3, 12,
CKE = HIGH; All banks active after
t
RCD met;
19, 26
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
I
DD
4
140
130
100
mA
3, 18,
READ or WRITE; All banks active, CAS latency = 3
19, 26
AUTO REFRESH CURRENT:
t
RC = 15.625s; CAS latency = 3;
I
DD
5
45
40
35
mA
3, 12,
CS# = HIGH; CKE = HIGH
18, 19,
26
SELF REFRESH CURRENT: CKE
0.2V
I
DD
6
1
1
1
mA
4
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
, V
DD
Q Supply
Relative to V
SS
................................ -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to V
SS
................................ -1V to +4.6V
Operating Temperature, T
A
(ambient) -40C to +85C
Storage Temperature (plastic) .......... -55C to +150C
Power Dissipation .................................................. 1W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
MAX
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
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31
16Mb: x16
IT SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11) (-40C
T
A
+85C)
AC CHARACTERISTICS
-6
-7
-8A
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
Access time from CLK (pos. edge)
CL = 3
t
AC
5.5
5.5
6
ns
CL = 2
t
AC
8
8.5
9
ns
22
CL = 1
t
AC
18
22
22
ns
22
Address hold time
t
AH
1
1
1
ns
Address setup time
t
AS
2
2
2
ns
CLK high level width
t
CH
2.5
2.75
3
ns
CLK low level width
t
CL
2.5
2.75
3
ns
Clock cycle time
CL = 3
t
CK
6
7
8
ns
23
CL = 2
t
CK
8
10
13
ns
22, 23
CL = 1
t
CK
20
25
25
ns
23
CKE hold time
t
CKH
1
1
1
ns
CKE setup time
t
CKS
2
2
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
1
1
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
2
2
2
ns
Data-in hold time
t
DH
1
1
1
ns
Data-in setup time
t
DS
2
2
2
ns
Data-out high-impedance time
CL = 3
t
HZ
5.5
5.5
6
ns
10
CL = 2
t
HZ
6
8.5
9
ns
10
CL = 1
t
HZ
18
22
22
ns
10
Data-out low-impedance time
t
LZ
1
1
1
ns
Data-out hold time
t
OH
1.5
1.5
1.5
ns
ACTIVE to PRECHARGE command
t
RAS
42
120,000
42
120,000
48
120,000
ns
AUTO REFRESH, ACTIVE command period
t
RC
60
70
80
ns
22
AUTO REFRESH period
t
RCAR
66
70
80
ns
ACTIVE to READ or WRITE delay
t
RCD
18
20
24
ns
22
Refresh period - 2,048 or 4,096 rows
t
REF
64
64
64
ms
PRECHARGE command period
t
RP
18
21
24
ns
22
ACTIVE bank A to ACTIVE bank B command
t
RRD
12
14
16
ns
Transition time
t
T
0.3
1.2
0.3
1.2
0.3
10
ns
7
WRITE recovery time
t
WR
1 + 4ns
1 + 3ns
1 + 2ns
t
CK
24
10
10
10
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
80
80
80
ns
20
CAPACITANCE
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
Input Capacitance: CLK
C
I
1
2.5
4.0
p F
2
Input Capacitance: All other input-only pins
C
I
2
2.5
5.0
p F
2
Input/Output Capacitance: DQs
C
IO
4.0
6.5
p F
2
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
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32
16Mb: x16
IT SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11) (-40C
T
A
+85C)
PARAMETER
SYMBOL
-6
-7
-8A
UNITS NOTES
READ/WRITE command to READ/WRITE command
t
CCD
1
1
1
t
CK
17
CKE to clock disable or power-down entry mode
t
CKED
1
1
1
t
CK
14
CKE to clock enable or power-down exit setup mode
t
PED
1
1
1
t
CK
14
DQM to input data delay
t
DQD
0
0
0
t
CK
17
DQM to data mask during WRITEs
t
DQM
0
0
0
t
CK
17
DQM to data high-impedance during READs
t
DQZ
2
2
2
t
CK
17
WRITE command to input data delay
t
DWD
0
0
0
t
CK
17
Data-in to ACTIVE command
CL = 3
t
DAL
5
5
5
t
CK
15, 21
CL = 2
t
DAL
4
4
4
t
CK
15, 21
CL = 1
t
DAL
3
3
3
t
CK
15, 21
Data-in to PRECHARGE
t
DPL
2
2
2
t
CK
16
Last data-in to burst STOP command
t
BDL
0
0
0
t
CK
17
Last data-in to new READ/WRITE command
t
CDL
1
1
1
t
CK
17
Last data-in to PRECHARGE command
t
RDL
1
1
1
t
CK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command
t
MRD
2
2
2
t
CK
26
Data-out to high-impedance from PRECHARGE command
CL = 3
t
ROH
3
3
3
t
CK
17
CL = 2
t
ROH
2
2
2
t
CK
17
CL = 1
t
ROH
1
1
1
t
CK
17
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
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33
16Mb: x16
IT SDRAM
12.Other input signals are allowed to transition no
more than once in any two-clock period and are
otherwise at valid V
IH
or V
IL
levels.
13.I
DD
specifications are tested after the device is
properly initialized.
14.Timing actually specified by
t
CKS; clock(s)
specified as a reference only at minimum cycle rate.
15.Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16.Timing actually specified by
t
WR.
17.Required clocks are specified by JEDEC functional-
ity and are not dependent on any timing param-
eter.
18.The I
DD
current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
19.Address transitions average one transition every
two-clock period.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on
t
CK = 166 MHz for -6, 143 MHz for -7
and 125 MHz for -8A.
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse
width
3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
IL
undershoot:
V
IL
(MIN) = -2V for a pulse width
3ns. The pulse
width cannot be greater than one third of the
cycle rate.
23.The clock frequency must remain constant during
access or precharge states (READ, WRITE, includ-
ing
t
WR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24.Auto precharge mode only.
25.Precharge mode only.
26.
t
CK = 6ns for -6, 7ns for -7, 8ns for -8A.
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
, V
DD
Q = +3.3V;
f = 1 MHz,
t
A = 25C.
3. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (-40C
T
A
+85C) is
ensured.
6. An initial pause of 100s is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously.
V
SS
and V
SS
Q must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the
t
REF refresh requirement is
exceeded.
7. AC characteristics assume
t
T = 1ns.
8. In addition to meeting the transition rate
specification, the clock and CKE must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
30pF
10.
t
HZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
V
OH
or V
OL
. The last valid data element will meet
t
OH before going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
=
3V with timing referenced to 1.5V crossover point.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
34
16Mb: x16
IT SDRAM
INITIALIZE AND LOAD MODE REGISTER
tCH
tCL
tCK
CKE
CLK
COMMAND
DQ
ADDRESS
BANK,
ROW
tRCAR
tMRD
tRC
AUTO REFRESH
AUTO REFRESH
Program Mode Register.
2, 3
tCMH
tCMS
Precharge
all banks.
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tRP
(
)
(
)
(
)
(
)
tCKS
Power-up:
V
DD
and
CLK stable.
T=100s
(MIN)
tAH
tAS
PRECHARGE
NOP
NOP
AUTO
REFRESH
NOP
LOAD MODE
REGISTER
ACTIVE
NOP
NOP
NOP
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
AUTO
REFRESH
BANK(S)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
High-Z
tCKH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQM
1
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON'T CARE
UNDEFINED
(
)
(
)
(
)
(
)
T0
T1
Tn + 1
To + 1
Tp + 1
Tp + 2
Tp + 3
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
MRD
2
2
2
t
CK
t
RC
60
70
80
ns
t
RCAR
66
70
80
ns
t
RP
18
21
24
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
*CAS latency indicated in parentheses.
NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
3. Outputs are guaranteed High-Z after command is issued.
16Mb: x16 IT SDRAM
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16MSDRAMx16IT.p65 Rev. 5/99
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35
16Mb: x16
IT SDRAM
POWER-DOWN MODE
1
tCH
tCL
tCK
Two clock cycles
CKE
CLK
DQ
All banks idle, enter
power-down mode.
Precharge all
active banks.
Input buffers gated off while in
power-down mode.
Exit power-down mode.
(
)
(
)
(
)
(
)
DON'T CARE
UNDEFINED
tCKS
tCKS
COMMAND
tCMH
tCMS
PRECHARGE
NOP
NOP
ACTIVE
NOP
(
)
(
)
(
)
(
)
All banks idle.
ADDRESS
BANK,
ROW
BANK(S)
(
)
(
)
(
)
(
)
High-Z
tAH
tAS
tCKH
tCKS
DQM
2
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
T0
T1
T2
Tn + 1
Tn + 2
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
NOTE: 1. Violating refresh requirements during power-down may result in loss of data.
2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
*CAS latency indicated in parentheses.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
36
16Mb: x16
IT SDRAM
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CLOCK SUSPEND MODE
1
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
tCH
tCL
tCK
tAC
tLZ
DQM
3
CLK
A0-A9
DQ
BA
A10
tOH
D
OUT
m
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
BANK
tDH
D
IN
e
tAC
tHZ
D
OUT
m + 1
COMMAND
tCMH
tCMS
NOP
NOP
NOP
NOP
NOP
READ
WRITE
DON'T CARE
UNDEFINED
CKE
tCKS tCKH
tCMH
BANK
COLUMN m
(A0 - A7)
2
COLUMN e
(A0 - A7)
2
tDS
D
IN
e + 1
NOP
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
37
16Mb: x16
IT SDRAM
AUTO REFRESH MODE
tCH
tCL
tCK
CKE
CLK
DQ
tRCAR
(
)
(
)
(
)
(
)
(
)
(
)
tRP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
COMMAND
tCMH
tCMS
NOP
NOP
(
)
(
)
(
)
(
)
BANK,
ROW
ACTIVE
AUTO
REFRESH
(
)
(
)
(
)
(
)
NOP
NOP
PRECHARGE
Precharge all
active banks.
AUTO
REFRESH
tRC
High-Z
ADDRESS
BANK(S)
(
)
(
)
(
)
(
)
tAH
tAS
tCKH
tCKS
(
)
(
)
NOP
DQM
1
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON'T CARE
UNDEFINED
T0
T1
T2
Tn + 1
To + 1
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
RC
60
70
80
ns
t
RCAR
66
70
80
ns
t
RP
18
21
24
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
*CAS latency indicated in parentheses.
NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
38
16Mb: x16
IT SDRAM
SELF REFRESH MODE
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self
refresh mode.
Precharge all
active banks.
tXSR
CLK stable prior to exiting
self refresh mode.
Exit self refresh mode.
(Restart refresh time base.)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON'T CARE
UNDEFINED
COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE
NOP
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
ADDRESS
BANK(S)
(
)
(
)
(
)
(
)
High-Z
tCKS
AH
AS
AUTO
REFRESH
> tRAS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tCKH
tCKS
DQM
1
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
t
t
tCKS
T0
T1
T2
Tn + 1
To + 1
To + 2
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RP
18
21
24
ns
t
XSR
80
80
80
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
*CAS latency indicated in parentheses.
NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
39
16Mb: x16
IT SDRAM
SINGLE READ WITHOUT AUTO PRECHARGE
1
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
*CAS latency indicated in parentheses.
ALL BANKS
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD
CAS Latency
tRC
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK
BANK(S)
BANK
ROW
ROW
BANK
tHZ
tCMH
tCMS
NOP
NOP
NOP
PRECHARGE
ACTIVE
NOP
READ
ACTIVE
NOP
DISABLE AUTO PRECHARGE
SINGLE BANKS
DON'T CARE
UNDEFINED
COLUMN m
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
DQM /
DQML, DQMH
CKE
CLK
A0-A9, A11
DQ
BA0, BA1
A10
COMMAND
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE.
2. A8, A9 = "Don't Care."
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
40
16Mb: x16
IT SDRAM
READ WITHOUT AUTO PRECHARGE
1
BANK 0 and 1
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD
CAS Latency
tRC
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK
BANK(S)
BANK
ROW
ROW
BANK
tHZ
tOH
D
OUT
m+3
tAC
tOH
tAC
tOH
tAC
D
OUT
m+2
D
OUT
m+1
COMMAND
tCMH
tCMS
PRECHARGE
NOP
NOP
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
DISABLE AUTO PRECHARGE
BANK 0 or 1
DON'T CARE
UNDEFINED
COLUMN m
(A0 - A7)
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
*CAS latency indicated in parentheses.
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
41
16Mb: x16
IT SDRAM
READ WITH AUTO PRECHARGE
1
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD
CAS Latency
tRC
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tOH
D
OUT
m
tAH
tAS
tAH
tAS
tAH
tAS
ROW
COLUMN
m
(A0 - A7)
2
ROW
BANK
BANK
ROW
ROW
BANK
DON'T CARE
UNDEFINED
tHZ
tOH
D
OUT
m + 3
tAC
tOH
tAC
tOH
tAC
D
OUT
m + 2
D
OUT
m + 1
COMMAND
tCMH
tCMS
tCMH
tCMS
NOP
NOP
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
*CAS latency indicated in parentheses.
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
42
16Mb: x16
IT SDRAM
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tAC
tLZ
DQM
3
CLK
A0-A9
DQ
BA
A10
tOH
D
OUT
m
tCMH
tCMS
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
COLUMN m
(A0 - A7)
2
ROW
ROW
ROW
DON'T CARE
UNDEFINED
tOH
D
OUT
m + 3
tAC
tOH
tAC
tOH
tAC
D
OUT
m + 2
D
OUT
m + 1
COMMAND
NOP
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tOH
D
OUT
b
tAC
tAC
READ
COLUMN b
(A0 - A7)
2
ENABLE AUTO PRECHARGE
ROW
ACTIVE
ROW
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0
CKE
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
tRP - BANK 0
tRAS - BANK 0
tRCD - BANK 0
tRCD - BANK 0
CAS Latency - BANK 0
tRCD - BANK 1
CAS Latency - BANK 1
t
t
RC - BANK 0
RRD
ALTERNATING BANK READ ACCESSES
1
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
t
RRD
12
14
16
ns
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
43
16Mb: x16
IT SDRAM
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
READ FULL-PAGE BURST
1
tCH
tCL
tCK
tAC
tLZ
tRCD
CAS Latency
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tOH
D
OUT
m
tCMH
tCMS
tCKH
tCKS
tCMH
tCMS
tAH
tAS
tAH
tAS
tAC
tOH
D
OUT
m+1
ROW
ROW
tHZ
tAC
tOH
D
OUT
m+1
tAC
tOH
D
OUT
m+2
tAC
tOH
D
OUT
m-1
tAC
tOH
D
OUT
m
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Full page completed.
256 locations within same row.
DON'T CARE
UNDEFINED
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
READ
NOP
BURST TERM
NOP
NOP
(
)
(
)
(
)
(
)
NOP
(
)
(
)
(
)
(
)
COLUMN m
(A0 - A7)
2
tAH
tAS
BANK
(
)
(
)
(
)
(
)
BANK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
4
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RCD
18
20
24
ns
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Page left open; no
t
RP.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
44
16Mb: x16
IT SDRAM
READ DQM OPERATION
1
tCH
tCL
tCK
tRCD
CAS Latency
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tCMS
ROW
BANK
ROW
BANK
DON'T CARE
UNDEFINED
tAC
LZ
D
OUT
m
tOH
D
OUT
m + 3
D
OUT
m + 2
t
tHZ
LZ
t
tCMH
tCMS tCMH
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
READ
NOP
NOP
NOP
tHZ
tAC
tOH
tAC
tOH
tAH
tAS
tAH
tAS
tAH
tAS
COLUMN m
(A0 - A7)
3
tCKH
tCKS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AC (3)
5.5
5.5
6
ns
t
AC (2)
8
8.5
9
ns
t
AC (1)
18
22
22
ns
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
HZ (3)
5.5
5.5
6
ns
t
HZ (2)
6
8.5
9
ns
t
HZ (1)
18
22
22
ns
t
LZ
1
1
1
ns
t
OH
1.5
1.5
1.5
ns
t
RCD
18
20
24
ns
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
45
16Mb: x16
IT SDRAM
SINGLE WRITE WITHOUT AUTO PRECHARGE
1
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
t
WR
10
10
10
ns
*CAS latency indicated in parentheses.
DON'T CARE
DISABLE AUTO PRECHARGE
ALL BANKS
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM /
DQML, DQMH
CKE
CLK
A0-A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK BANK
BANK
ROW
ROW
BANK
t WR
D
IN
m
tDH
tDS
COMMAND
tCMH
tCMS
ACTIVE
NOP
WRITE
NOP
PRECHARGE
ACTIVE
tAH
tAS
tAH
tAS
SINGLE BANK
tCKH
tCKS
COLUMN m3
2
T0
T1
T2
T4
T3
T5
T6
NOP
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE.
2. 10ns is required between <D
IN
m> and the PRECHARGE command, regardless of frequency, to meet
t
WR.
3. A8, A9 = "Don't Care."
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
46
16Mb: x16
IT SDRAM
WRITE WITHOUT AUTO PRECHARGE
1
DISABLE AUTO PRECHARGE
BANK 0 and 1
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tCMH
tCMS
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK
BANK(S)
BANK
ROW
ROW
BANK
t WR
4
DON'T CARE
UNDEFINED
D
IN
m
tDH
tDS
D
IN
m + 1
D
IN
m + 2
D
IN
m + 3
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
WRITE
NOP
PRECHARGE
ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS
tDH
tDS
tDH
tDS
BANK 0 or 1
COLUMN
m
(A0 - A7)
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
t
WR
10
10
10
ns
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by "manual" PRECHARGE.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Faster frequencies will require two clocks (when
t
WR >
t
CK).
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
47
16Mb: x16
IT SDRAM
WRITE WITH AUTO PRECHARGE
1
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tCMH
tCMS
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK
BANK
ROW
ROW
BANK
tWR
4
DON'T CARE
UNDEFINED
D
IN
m
tDH
tDS
D
IN
m + 1
D
IN
m + 2
D
IN
m + 3
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS
tDH
tDS
tDH
tDS
COLUMN
m
(A0 - A7)
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
t
WR
1 + 4ns
1 + 3ns
1 + 2ns
t
CK
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Faster frequencies will require two clocks (when
t
WR >
t
CK).
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
48
16Mb: x16
IT SDRAM
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tCH
tCL
tCK
CLK
DQ
DON'T CARE
UNDEFINED
D
IN
m
tDH
tDS
D
IN
m + 1
D
IN
m + 2
D
IN
m + 3
COMMAND
NOP
NOP
ACTIVE
NOP
WRITE
NOP
ACTIVE
tDH
tDS
tDH
tDS
tDH
tDS
ACTIVE
WRITE
tDH
tDS
D
IN
b + 1
D
IN
b + 2
tDH
tDS
tDH
tDS
ENABLE AUTO PRECHARGE
DQM
3
A0-A9
BA
A10
tCMH
tCMS
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
COLUMN m
(A0 - A7)
2
ROW
ROW
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
BANK 0
BANK 0
BANK 1
BANK 0
BANK 1
CKE
tCKH
tCKS
COLUMN b
(A0 - A7)
2
D
IN
b
T0
T1
T2
T3
T4
T5
T6
T7
T8
tRP - BANK 0
tRAS - BANK 0
tRCD - BANK 0
tRCD - BANK 0
tWR - BANK 0
4
tRCD - BANK 1
t
t
RC - BANK 0
RRD
ALTERNATING BANK WRITE ACCESSES
1
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RAS
42
120,000
42
120,000
48
120,000
ns
t
RC
60
70
80
ns
t
RCD
18
20
24
ns
t
RP
18
21
24
ns
t
RRD
12
14
16
ns
t
WR
1 + 4ns
1 + 3ns
1 + 2ns
t
CK
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Faster frequencies will require two clocks (when
t
WR >
t
CK).
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
49
16Mb: x16
IT SDRAM
WRITE FULL-PAGE BURST
tCH
tCL
tCK
tRCD
DQM
2
CKE
CLK
A0-A9
BA
A10
tCMS
tAH
tAS
tAH
tAS
ROW
ROW
Full-page burst does not
self-terminate. Can use
BURST TERMINATE command.
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Full page completed.
256 locations within
same row.
DON'T CARE
UNDEFINED
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
WRITE
BURST TERM
NOP
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQ
D
IN
m
tDH
tDS
D
IN
m + 1
D
IN
m + 2
D
IN
m + 3
tDH
tDS
tDH
tDS
tDH
tDS
D
IN
m - 1
tDH
tDS
tDH
tDS
COLUMN m
(A0 - A7)
1
tAH
tAS
BANK
(
)
(
)
(
)
(
)
BANK
tCMH
tCMS tCMH
tCKH
tCKS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
3
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RCD
18
20
24
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
*CAS latency indicated in parentheses.
NOTE: 1. A8 and A9 = "Don't Care."
2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
3. Page left open; no
t
RP.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
50
16Mb: x16
IT SDRAM
tCH
tCL
tCK
tRCD
DQM
3
CKE
CLK
A0-A9
DQ
BA
A10
tCMS
tAH
tAS
ROW
BANK
ROW
BANK
ENABLE AUTO PRECHARGE
D
IN
m + 3
tDH
tDS
D
IN
m
D
IN
m + 2
tCMH
tCMS tCMH
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
WRITE
NOP
NOP
DON'T CARE
UNDEFINED
tDH
tDS
tDH
tDS
tAH
tAS
tAH
tAS
DISABLE AUTO PRECHARGE
COLUMN m
(A0 - A7)
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
WRITE DQM OPERATION
1
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
CKH
1
1
1
ns
t
CKS
2
2
2
ns
t
CMH
1
1
1
ns
t
CMS
2
2
2
ns
t
DH
1
1
1
ns
t
DS
2
2
2
ns
t
RCD
18
20
24
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AH
1
1
1
ns
t
AS
2
2
2
ns
t
CH
2.5
2.75
3
ns
t
CL
2.5
2.75
3
ns
t
CK (3)
6
7
8
ns
t
CK (2)
8
10
13
ns
t
CK (1)
20
25
25
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. A8 and A9 = "Don't Care."
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
51
16Mb: x16
IT SDRAM
50-PIN PLASTIC TSOP (400 mil)
C-4
0.10
10.21
10.11
0.45
0.30
0.80
TYP
2.80
50
1
25
SEE DETAIL A
1.2
MAX
0.25
DETAIL A
GAGE PLANE
PIN #1 ID
R 1.00 (2X)
R 0.75 (2X)
0.25
0.05
0.18
0.13
21.04
20.88
11.86
11.66
0.80
TYP
0.60
0.40
0.10 (2X)
0.88
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
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